On the left, from 1995, J32, one 32-bit RISC SoC in an XC4010. It had 20x20x2=800 4-LUTs (and 400 3-LUTs).
On the right, from 2013, 1000 32-bit RISC datapaths and 250 router cores in an XC7VX690T (which provides over 433,000 6-LUTs and 1470 BRAMs). A work in progress.
In other words, in the past 18 years Moore’s Law has taken us from 1K LUTs per FPGA to 1K 32-bit CPUs per FPGA.
At FCCM 2013, I was on a panel to discuss Reconfigurable Computing in the Era of Dark Silicon. If you haven’t heard of the Dark Silicon meme in the computer architecture community, I recommend you review Michael Taylor (UCSD)‘s slides from DaSi 2012.
It’s difficult to take these things out of context, but here for posterity’s sake are my position slides: Gray-Dark Silicon and HeMPPAAs. I emphasize that orders of magnitude energy efficiency improvements might be achieved by building workload-optimized computers in FPGAs using a HeMPPAA (heterogeneous massively parallel processor and accelerator arrays) architecture. I also propose infrastructure investments so that FPGA design in the large is much more like the software development experience.
Disclaimers: I am sharing what works for me. It may not work for you or it may fail over time. You may suffer data loss or worse. I disclaim all warranties and representations. I am not supporting this. I am not a Linux kernel hacker.
Update (Sept 18, 2013): In the 8th comment to this article, commentor eactor notes these months-old instructions may be getting stale. He/she says “The kernel has evolved over the past month, I successfully used your instructions to build a running linaro (Kernel 3.8) with git checkout xcomm_zynq_3_8” — but not using git checkout xcomm_zynq. So until I can revisit this article and verify this, you may wish to try git checkout xcomm_zynq_3_8 below rather than git checkout xcomm_zynq.
After all, isn’t Zynq for embedded systems? Most don’t need desktop UIs. Isn’t cross development faster? And if you need a UI surely Android is a better choice?
Yes, it’s not fast. But it’s fast enough. I don’t trust it. But it seems stable. Certainly it stays up all day and runs complex software builds (e.g. OpenCV).
Mostly it’s the pinch myself factor. It is remarkable that using an FPGA you can boot, have a UI, get on the internet, easily take advantage of the universe of web services and local open source software. Also by living on ZedBoard you will learn the vagaries and limitations of the platform. Eating your own dogfood.
Of related interest (feel free to skip this section). Just a history of things I’ve looked into.
“Preparing the SD Card
To boot the system on the ZED or ZC702 board you’ll need a SD memory card. The SD card should have at least 4 GB of storage and it is recommended to use a card with speed-grade 6 or higher to achieve optimal file transfer performance. … The SD card needs to be partitioned with two partitions. The first one should be about 40MB in size and the second one should take up the remaining space. For optimal performance make sure that the partitions are 4MB aligned. The first partition needs to be formatted with a FAT filesystem. It will hold the bootloader, devicetree and kernel images. The second partition needs to be formatted with a ext4 filesystem. It will store the systems root filesystem.”
+ "sdboot=echo Copying Linux from SD to RAM...;"
+ "mmcinfo;"
+ "fatload mmc 0 0x3000000 ${kernel_image};"
+ "fatload mmc 0 0x2A00000 ${devicetree_image};"
+ "bootm 0x3000000 - 0x2A00000"
“Build the boot image
To complete this step you need to have a u-boot image for the Zynq platform. Please refer to the Xilinx wiki on how to build such an image. [[Rather — see above instructions.]]
The bootloader can be build with Xilinx SDK. In order to do so it is necessary to first export the HDL design from the Xilinx Platform Studio to the SDK, this is done by clicking the “Export to SDK” button in the Platform Studio GUI.
Export project to SDK: …
Once the project has been exported create a new FSBL project in the SDK. To do this right-click on the newly exported hardware platform specification in left “Project Explorer” panel and select “New > Project” from the popup menu. Select “Xilinx – Application Project” on first dialog page. On the second dialog page choose a name for the project (zynq_fsbl for example) and on the third page select “Zynq FSBL” template.
The project should build automatically. If not a manual build can be started by right clicking the newly created project in the left “Project Explorer” pane and selecting “Build Project” from the popup menu. After the project has been build it is time to generate the boot image. This is done by right clicking on the project in the left “Project Explorer” pane and selecting “Create Boot Image”. This will open up the bootgen wizard. The bootgen wizard needs three files:
The freshly build zynq_fsbl.elf binary
The system.bit bitstream
The u-boot.elf binaryAdd these files to partitions list in the dialog, then select an output folder.
Clicking “Create Image” will now generate in the chosen location a new boot image for the target platform. The output *.bin file should be renamed “BOOT.BIN” and needs to be saved on the first partition of the SD-card .” [[e.g. the BOOT partition mounted at /media/BOOT]]
// bootargs = "console=ttyPS0,115200 root=/dev/ram rw initrd=0x1100000,33M ip=:::::eth0:dhcp earlyprintk"; bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait devtmpfs.mount=0";
“Once all of the previous tasks have been completed it is time to test the system. To do this inserted the SD-card into the board and power-up the board. After a few seconds the blue “DONE” LED should light up. This means that the bitstream has been successfully loaded and the system will now start to boot. It is also possible to connect to the serial console by using the on-board UART-to-USB bridge, this allows to monitor the boot process and view debug messages.
After another few seconds the monitor connected to the system will turn on and display the Linux mascot in the top left corner, after that the Ubuntu Desktop system will appear on the screen. The system is now ready to be used.”
Visual C++ on Windows NT on Bochs on Linaro Ubuntu Linux on Xilinx Zynq on ZedBoard
Max Maxfield, Editor in Chief of the new UBM/Xilinx site All Programmable Planet:
“We are interested in all the things that have to do with programmable “stuff.” … All this explains why any system architect or hardware design engineer looking at creating any form of electronic system or product now includes programmable devices in all their forms in the deliberations.”
Notice also the same marketing slogan at xilinx.com: “All Programmable technologies and devices”. No longer mere programmable logic.
I speculate that this is a new community site for Xilinx users which, with the launch of Zync EPP and Vivado high level tools and the roll-out of 7 Series devices, will drive new marketing messaging that repositions Xilinx products: as mainstream system design platforms and tools, applicable to any problem. No longer are FPGAs just for glue, low volume ASIC prototyping, routers, base stations, or custom accelerators. No longer are they relegated to the data plane, subordinate to some other embedded processor SoC. Rather with arrival of Zync, start to think of their product line as fast time-to-market platforms and tools for developing and shipping complete integrated systems, including volume consumer electronics. Expect to see a much greater emphasis on high level software assets — preported OSs (Linux, Android, …), applications frameworks (TV, automotive, medical), and targeted design platforms and kits, and more product love for embedded systems designers and software developers.
Xilinx has picked an apt slogan that nicely captures the value proposition of its programmable logic All Programmable platforms.
UPDATE: See also the Xilinx Company Overview page which makes this quite explicit. Xilinx technologies have evolved from “Programmable Logic Devices”; now “All Programmable Devices Enables Programmable Systems ‘Integration'”.
In 2010 and 2011 I gave this survey talk on prospects for continued exponential scaling of computer performance for the Singularity University Graduate Studies Program, in Mountain View, CA.
It is in three parts: prospects for continued transistor scaling; the transition to parallel computer architecture; and the challenges of writing mainstream software for parallel computers.
It has been about nine years since my last blog post at FPGA CPU News. How’s that for taking a break?
Back then I returned to Microsoft as a performance architect on the .NET Common Language Runtime. (Example.) Around 2004 it became clear that clock frequency scaling was at its asymptotic end and future performance scaling would increasingly come from parallel computing. I spent the next five years working to get Microsoft’s client software stack, and in particular its developer platform and tools ready for mainstream multi-core, manycore, and heterogeneous platforms. My mission was “to provide loveable parallel programming models, tools, and infrastructure that enable any developer to write robust software that scales up on new hardware”. I led a product incubation on transactional memory and 2007-09 I helped define and build Microsoft’s Parallel Computing Platform strategy, team, and software, some of which shipped in Visual Studio 2010.
I have missed blogging. I microblog on twitter, but it does not afford the space to elaborate on a topic.
The main theme of this blog is implementing parallel computers in FPGAs, but I will also use this space to sound off on other matters of interest to me.
For starters I am going to bring forward the archived FPGA CPU News content, bit by bit. Unfortunately the old site was just a big sed script so there is no good automated solution. I will fix linkrot where I can. Otherwise dead links will get dead-url’d and struck out. These articles should follow in reverse chronological order.
For the time being, the old archived site is at http://fpgacpu.org and this site will be at https://fpga.org. When I finish importing the archived content, I will remove the old site (both will point here).
Thank you for visiting.
Ron Wilson, EE Times: Avoidance proposed as solution to 90-nm problems. Very interesting.
“The notion that RTL must be a description of the wiring, not simply an expression of the logic, recurred during the panel. It has also been voiced frequently by design teams (not represented on the panel) that are working with 130-nm designs. …””The notion of the predesigned, configurable platform is beginning to get serious notice at 90 nm.”
Happy new year (belated).
Embrace change Anthony Cataldo, EE Times: Altera to spin new FPGA for 90-nm production
Altera: Cyclone Devices … Shipping Ahead of Schedule.
“With only 15 months from conception to shipment, the development of the Cyclone device family is the fastest in Altera’s history.”
Altera: … Delivery of First Stratix GX Devices. Now sampling.
Impressive. Congratulations. Execute, execute, execute.
Xilinx: Enables Gibson Guitar’s Best of Show Award. I saw this at CES. A guitar with an ethernet jack.
“Gibson will offer MaGIC, an acronym for Media-accelerated Global Information Carrier, in every Gibson guitar within the next 12-18 months. …””MaGIC uses state-of-the-art technology to provide up to 32 channels of 32-bit bi-directional high-fidelity audio with sample rates up to 192 kHz. Data and control can be transported 30 to 30,000 times faster than MIDI.”
Tom Hawkins of Launchbird Design Systems, Inc. announces Confluence 0.1.
“Confluence is a simple, yet amazingly powerful hardware design language. Its flexibility and high level of expression reduces code size and complexity of a design when compared with either Verilog or VHDL. Confluence also enforces clean RTL preventing common errors and bad design practices often introduced in traditional HDL coding.””And unlike C based approaches, design engineers love Confluence because it still feels like coding in HDL. The language is implicitly parallel and very structural. …”
“Confluence runs on Linux x86.”
OK, but please let us know when you run on the volume platform. Does Confluence employ OCaml? Interesting if so. So far, details sketchy, but welcome, the more, the merrier.
Today’s schedule of the SDRForum Symposium on Use of Reconfigurable Logic in Software Defined Radios.
FPGA-FAQ has a nice fresh list of FPGA boards.
Peter Clarke, Semiconductor Business News: Former UK defense unit offers floating-point unit for FPGAs. For MicroBlaze and the Virtex-II Pro’s PowerPC(s). QinetiQ [Quixilica].
‘We’re already seeing applications in image and signal processing systems, control, and support of legacy hardware, where the combination of an FPGA with an embedded microprocessor core and the FPU can provide the functionality and performance of an entire DSP subsystem, said Bill Smith, manager of QinetiQ’s real-time systems laboratory, in statement.’
I’ve been to Malvern several times, lovely place.
Thanks, Joe Strummer.