It has been about nine years since my last blog post at FPGA CPU News. How’s that for taking a break?

Back then I returned to Microsoft as a performance architect on the .NET Common Language Runtime. (Example.) Around 2004 it became clear that clock frequency scaling was at its asymptotic end and future performance scaling would increasingly come from parallel computing. I spent the next five years working to get Microsoft’s client software stack, and in particular its developer platform and tools ready for mainstream multi-core, manycore, and heterogeneous platforms. My mission was “to provide loveable parallel programming models, tools, and infrastructure that enable any developer to write robust software that scales up on new hardware”. I led a product incubation on transactional memory and 2007-09 I helped define and build Microsoft’s Parallel Computing Platform strategy, team, and software, some of which shipped in Visual Studio 2010.

I have missed blogging. I microblog on twitter, but it does not afford the space to elaborate on a topic.

The main theme of this blog is implementing parallel computers in FPGAs, but I will also use this space to sound off on other matters of interest to me.

For starters I am going to bring forward the archived FPGA CPU News content, bit by bit. Unfortunately the old site was just a big sed script so there is no good automated solution. I will fix linkrot where I can. Otherwise dead links will get dead-url’d and struck out. These articles should follow in reverse chronological order.

For the time being, the old archived site is at http://fpgacpu.org and this site will be at https://fpga.org. When I finish importing the archived content, I will remove the old site (both will point here).

Thank you for visiting.