Lauro Rizzatti, in EEdesign: Gates, lies and common sense. Rizzatti revisits the marketing gates issue.
“Realistically, now there is a simple, practical way to compare the design capacity of two emulation solutions based on the Virtex-II components. By listing type and quantity of Virtex-II devices allocated to mapping the design-under-test, possibly augmented by one or more external memory banks, you can now truthfully and reliably evaluate two or more emulation systems.”
Well that’s not very helpful. Far better is to simply describe a capability vector of total resources. Then you can compare across families and across vendors.
The vector should include (#LUTs, tILO, amt. of each layer of memory hierarchy, external RAM). Thus a system with two XC2V6000-5’s might be
(68 KLUT, 410 ps, 1056 Kb LUT RAM, 2.6 Mb BRAM, ?) * 2 => (135 KLUT, 410 ps, 2 Mb LUT RAM, 5.2 Mb BRAM, ?)
and a system with four EP1S60s might be something like
(57 KLUT, ? ps, 574 M512s, 292 M4096, 6 MegaRAM, ?) * 4 => (228 KLUT, ? ps, 1.1 Mb M512s, 4.6 Mb M4096s, 13.5 Mb MegaRAM, ?).
If your problem domain warrants it, by all means, grow the capability vector to include multiplier resources, embedded processors, high speed serial resources, etc.
Congratulations to Altera for simply naming their new parts with the most imortant element of this capability vector, KLUTs.