Category Archives: GRVI Phalanx

GRVI Phalanx Update Presentation at the 7th RISC-V Workshop

On Nov. 29, 2017, I gave a talk titled GRVI Phalanx Update: Plowing the Cloud with Thousands of RISC-V Chickens (PDF) at the 7th RISC-V Workshop.

In this talk for the RISC-V community I recap the purpose, design, and implementation of the GRVI Phalanx Accelerator Kit, recent work, and present work in progress to deliver an SDK for AWS EC2 F1 and PYNQ-Z1, including an OpenCL-like programming model built upon Xilinx SDAccel.

GRVI Phalanx on AWS F1 — die plots of various work-in-progress XCVU9P F1 designs including: 0 cores with 4 DDR4 DRAM channels, 884 cores with 3 channels, 1240 cores with 1 channel, and 9920 cores (8 FPGA slots, on AWS F1.16xlarge).